Jell AICAN decides at run time who may transmit, by arbitration. FlexRay decides in advance. Every node knows from a shared schedule exactly when it may send, so the timing of a frame does not depend on the rest of the traffic. FlexRay was developed for applications with strict safety, reliability and real-time requirements, and it shows up in time-triggered chassis and safety networks.
BMW and DaimlerChrysler founded the FlexRay Consortium with Motorola and Philips in 2000, aiming for a deterministic, fault-tolerant standard that carmakers could use without licence fees. The first production vehicles with FlexRay appeared in 2006. The consortium published version 3.0.1 of the specification in 2010, and ISO published FlexRay as ISO 17458 in 2013.
Two channels at 10 Mbit/s
Each node can connect to two channels, A and B, in a line, passive star or active star topology. Each channel is a differential pair, Bus Plus and Bus Minus, terminated with 80 to 110 Ω. At idle both lines sit at about 2.5 V. A 1 drives Bus Plus to about 3.5 V and Bus Minus to about 1.5 V, a 0 the other way round, so the differential voltage swings between +2 V and −2 V. Each channel runs at up to 10 Mbit/s. The two channels can carry the same frames for redundancy, or different frames for up to 20 Mbit/s in total. And because FlexRay has no bitwise arbitration, its bit rate does not depend on the length of the network.
The communication cycle
Time in a FlexRay cluster is divided into communication cycles of fixed length that repeat, counted from 0 to 63 and then from 0 again. A cycle always contains a static segment and a network idle time, and may also contain a dynamic segment and a symbol window.
- Static segment: slots of equal length, up to 1023 per channel. In each cycle a slot belongs to one node, and a frame’s ID is the number of its slot. All static frames have the same payload length. Because each frame is also defined by a base cycle and a repetition, a node can send different frames in the same slot in different cycles, for example one in even and another in odd cycles.
- Dynamic segment: a fixed length of short minislots. A counter steps through them, and a node whose frame ID matches the counter may send, if it has data and the frame still fits; its frame then occupies as many minislots as it needs. Otherwise one minislot goes by empty. Lower frame IDs therefore get the first chance in every cycle.
- Symbol window and network idle time: no ordinary frames. The symbol window carries symbols such as the wake-up symbol, and in the network idle time the nodes correct their clocks before the next cycle.
A common clock
A schedule only works if every node agrees on the time. Selected nodes send sync frames in the static segment; every node compares when they arrive with when it expected them and corrects its own clock. Each node counts time in macroticks, which are synchronized across the cluster, built from microticks of its own local oscillator.
The frame
A FlexRay frame has a 40-bit header, up to 254 bytes of payload and a 24-bit CRC. The header holds a reserved bit and four indicator bits, among them the sync frame and startup frame indicators; the 11-bit frame ID; the payload length in 2-byte words; an 11-bit header CRC over the ID, the payload length and the sync and startup indicators; and the 6-bit cycle count. A node that has no valid data for its static slot still transmits, as a null frame whose payload is all zeros and whose null frame indicator marks it as such.
FlexRay on a test rig
A FlexRay rig has to join the schedule. It transmits the frames of the nodes that are not on the bench in exactly their slots, on the right channels, locked to the cluster’s time. If the ECU on the bench cannot start the cluster on its own, the rig also provides the coldstart and sync nodes that bring it up and keep it synchronized. We integrate FlexRay into real-time systems with the schedule, frames and signals taken from the cluster description, together with fault injection such as missing frames, null frames and wrong signal values. If you are planning a FlexRay rig, get in touch.
Sources
- Vector, FlexRay course: history, frame header, frame payload
- Texas Instruments, FlexRay Module Training, SPRT718
- P. S. Murvay, Politehnica University of Timișoara, FlexRay lecture, after the FlexRay specification 3.0.1
- Pico Technology, A deep dive into FlexRay: architecture, voltage levels and packet structure
- B. Tanasa, U. D. Bordoloi, P. Eles, Z. Peng, Probabilistic Timing Analysis for the Dynamic Segment of FlexRay, ECRTS 2013
- Z. Hanzálek et al., Czech Technical University, FlexRay scheduling (base cycle and cycle repetition)